problem 4 and 5
1. Draw the synthesized logic resulting from the following VHDL code. Label all the signals on your diagram precisely entity unknown is generic (k: natural: 3) port (x in std_logic_vector (2″k-1 downto 0); f: out std logic); end unknown; architecture struct of unknown is component and2 is port (a, b: in std_logic; c: out std_logic) end component component or2 is port (a, b: in std_logic; c: out std_logic) end component type matrix is
