13. Design a synchronous counter for the count sequence 0,1,2,3,2,1, 0,1,2,3,2,1, 0,..,where 0,1,2,3,2,1 will be the repeating sequence. In your design, you are allowed to use only a minimum number of JK fAlip-flops and NOR gates. Assume that initially the outputs of all flip-flops are O. Logic levels 1 and 0 are available. The count sequence will be obtained at the flip-flop outputs. Show transcribed image text 13. Design a synchronous counter for the count sequence 0,1,2,3,2,1, 0,1,2,3,2,1, 0,..,where 0,1,2,3,2,1 will
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