2. (10 points) Suppose that an unpipelined processor has a cycle time of 25 ns, and its datapath consists f modules with the latencies of 2, 3, 4, 7, 3, 2, and 4 ns (in this specific order). In pipelining this processon, it is not possible to rearrange the order of the modules (for example, putting the register read stage before the instruction decode stage) or to divide a module into multiple pipeline stages
OR
OR