2. Given a direct mapped cache with 4 blocks, a two-way associative cache with 2 blocks in each set and a fully associative cache with 4 blocks Com pute the number of hits and misses in each cache for accessing the following memory addresses (3*5-15) 100, 101, 102, 105, 106, 107, 108, 110, 112 Show transcribed image text 2. Given a direct mapped cache with 4 blocks, a two-way associative cache with 2
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