3 Consider Direct Mapped Cache Architecture Byte Addressable Cache 4 Lines Row Hold One By Q37105467

3. Consider a direct-mapped cache. The architecture is byte-addressable. The cache has 4 lines, and each row can hold one byte. The system is in cold-start. Read the whole problem before starting (a) (5 points) Fill out the missing elements in the table below Op Addr. Hit or miss?Any writes to another part of cache? LB 0x8CB LB 0x8C5 LB 0x8CA LB 0x8C2 SB0x8CA LB0x8C2 LB 0x8C6 LB 0x8C4 (b) (4 points) Give a table profiling

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