3 Direct Mapped Cache Design 32 Bit Address Following Bits Address Used Access Cache Tag I Q37092891

Please show your work and answer all parts correctly

3- for a direct mapped cache design with a 32 bit address, the following bits of address are used to access the cache Tag Index Offset 31-10 9-5 4-0 a. What is cache block size (in word)? b. How many entries does the cache have? c. What is the ration between total bits required for such a cache implementation one the data storage bits?

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