4.) (20 pts.) Consider the following instruction, as discussed in Example 8.6: 1 MAC *AR2+, *AR3+, A Suppose the processor has three ALUs, one for each arithmetic operation on the addresses contained in registers AR2 and AR3 and one to perform the addition in the MAC multiply-accumulate instruction. Assume these ALUs each require one clock cycle to execute. Assume that a multiplier also requires one clock cycle to execute. Assume further that the register bank supports
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