5.3 For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache Tag Index Offset 31-10 9-5 4-0 5.3.1 [5] <$5.3> What is the cache block size (in words)? 5.3.2 [5] <$5.3> How many entries does the cache have? 5.3.3 [5] <$5.3> What is the ratio between total bits required for such a cache implementation over the data storage bits? Show transcribed image text 5.3
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