7 Complete Vhdl Text File 74ls194a Universal Bi Directional Shift Register Entity Q7 Port Q37242076

7. Complete the VHDL text file below for the 74LS194A universal, bi- directional shift register. ENTITY q7 IS PORT( CLK, CLR : ABCD SR, SL, S1,S0 BUFFER (3 DOWNTO 0) END q7 ARCHITECTURE OF IS BEGIN PROCESs ( BEGIN IF THEN Q “0000”; <- ELSIF CLK’ EVENT AND CLKO’ THEN IF S1 = ‘0’ AND SO ‘0’ THEN ELSIF S1 – AND THEN ELS I F S1 AND SO THEN ELS 1 F s1 = Q

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