Assume a classic 5-stage in-order pipelined CPU that uses the asimplified MIPS-32 ISA with no forwarding (the system stallsinstead) and a perfect memory system (eg: all memory referencestake 1 cycle.) First identify data hazards in the followingassembly. Second, which column is faster and why? Here are the twoinstructions used:
LD $base, $dest, offset → $dest = Memory[$base+ offset]
ADD $src1, $src2, $dest → $dest = $src1 +$src2
A
B
LD $0, $1, 1024
LD $1, $2, 4
LD $2, $3, 4
ADD $1, $3, $4
ADD $4, $2, $4
LD $0, $1, 1024
LD $0, $2, 1028
LD $0, $3, 1032
ADD $1, $2, $4
ADD $4, $3, $4
Answer