Assume that the operation times for the major functional unitsin the Single -Cycle implementation are the following;
a) Instruction Memory Unit: 2 ns
b) Data Memory Unit (Read): 3 ns
c) Data Memory Unit (Write): 4 ns
d) ALU: 2 ns
e) PC + 4 Adder: X ns
f) Branch address computation Adder: Y ns
g) Register File (Read): 1 ns
h) Register File (Write): 2 ns
Assuming that Multiplexors, Sign-Extension Units and Wires havenegligible delays, find the total delay of eachlw,sw,add,sub,and,or,slt. Show in tabular form.
PS: Find the delays by drawing the data path for each individualinstruction
Answer