Consider the code sequence below in executing on an SMP systemwith 2 processors implemented with a snooping bus. The system usesMSI protocol. Assume R2 is initialized to 0x0200 on both processorsin cycle C0. ISA format:
Fill in the status of the cache line for the address 0x0200 foreach cycle for both processors. In MSI protocol, a cache line canbe I (Invalid), S (Shared), or M (Modified) state.
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