Develop Model Capture Performance Penalty Differences Cache Miss D Cache Miss Pipeline Ass Q37211246

You are to develop a model to capture the performance penaltydifferences from an I-cache miss and a D-cache miss for thispipeline. Assume, that the ideal CPI of the machine is onlyaffected by these two types of cache misses, so you can ignorebranch mis-prediction, exception, TLB misses, and so forth. Developa model reflecting the functional characteristics of anOut-of-Order machine. You may assume:

1. The issue width of the machine is I.
2. The Re-order buffer size of the machine is R.
3. The Instruction Window of the machine is W.
4. Miss-penalty cycles of an I-cache miss and D-cache miss areidentical – M
5. Any other application/hardware characteristics you want
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