Implement Data Memory Block Single Cycle Micro Architecture Vhdl Verilog Memory One Read P Q37023559

Implement the Data Memory block from the Single cyclemicro-architecture in VHDL/Verilog.

The memory has one read port and one write port. Data is writteninto the memory when clock is high and write enable is high. Also,check for invalid memory address and print out a error message whenthe program tries to write into a reserved memory address. (This issimilar to the MIPS memory map).

Solution