Module Maindec Input Logic 5 0 Op Output Logic Memtoreg Memwrite Output Logic Branch Alusr Q37150480

Please create a testbench for this module. Create it in systemverilog language

module maindec (input logic [5:0] op, output logic memtoreg, memwrite, output logic branch, alusrc, output logic regdst, regwrite, output logic jump, output logic [1:0] aluop); logic [8:0] controls; assign {regwrite, regdst, alusrc, branch, memwrite, memtoreg, jump, aluop} – controls; always_comb case(op) 6″b000000: controls9″b110000010; // RTYPE 6’b10001 1 : controls <= 9.b101001000; // LW 6’b101011: controls-9’b001010000; I/ SW 6″b000100: controls 9′ b000100001; // BEQ 6 “b001000: controls <-9’b101000000 /I

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