A particular 128 M-bit square memory array has its peripheral circuits reorganized to allow for the readout of a 64-bit double-double word. How many address bits will the new design need? (2000) Show transcribed image text A particular 128 M-bit square memory array has its peripheral circuits reorganized to allow for the readout of a 64-bit double-double word. How many address bits will the new design need? (2000)
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