- Preparation
- Write truth table of AND3 logic
- Draw a schematic of AND3 using PMOS, NMOS.
- Draw three pulse waveforms needed to test AND3 (3 inputs)circuit, assuming the following:
- Cycle time/period among the 3 pulses is 240ps
- Rise time is fixed at 10ps
- Fall time is fixed at 10ps
- You need to select different pulse widths so that you can cover2^3( 2 to the power of 3)=8 cases for AND logic.
- Indicate pulse widths clearly in your waveforms.
- Mark 8 cases,(000,001, etc) in the very bottom of your graphclearly too.
- Your waveforms should be symmetrical in shape that has apositive pulse width equal to its negative pulse width resulting ina 50%
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