Problem: Design a sequence detector with an active low output, z, that detects the sequence “101” on input w. The detect additional input, non/over, that determines whether it detects non- overlapping (non/over0) or overlapping (non/over 1) sequences A) Draw the finite state diagram B) Write the state table. Using Quartus, write the VHDL that implements the detector C) Using ModelSim, test your detector and confirm functionality. Make sure that the input signal does not change
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