Question 1 6 pts You are tasked with converting a combinational component connected to a register into a pipelined implementation. Currently, the combinational component has a propagation delay of 350 picoseconds (ps). The register has a delay of 10 ps. After several refinements, you are able to pipeline the combinational component into five stages; each stage has a propagation delay of 70 ps. Answer the following questions (enter only numeric values What would be the minimum clock
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