Write Verilog Program Verify Using Test Benches Using Monitor Display Strobe Provide Outpu Q37142663

Write Verilog program, verify using test benches usingmonitor/display/strobe and provide output for the followingprograms.

10

@(clk) q=d; (clk, rst)q- d (clk or rst) q di (posedge clk) q-di (negedge clk) q-di – (posedge clk) di always () y = (a & b) | (c & d)

OR

 

OR